1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having such a structure that a semiconductor chip is mounted on a mount body, and a method of manufacturing the same.
2. Description of the Related Art
The problems such as reduction in yield, an increase in mounting area, and high-cost promotion have been serious along with the high integration promotion, the high performance promotion and the high function promotion of the LSIs (Large Scale Integration). In recent years, a System-in-Package (SiP) in which these problems and the LSI performance can be made compatible with each other has attracted attention. The SiP can be classified into various kinds of structures such as a package lamination type one, a chip stack type one, and a Chip-on-Chip type one. In particular, the Chip-on-Chip type SiP has an advantage to speed up the operation and to reduce the power consumption because the Chip-on-Chip type SiP allows chips to undergo multiple pin connection with a short wiring length.
The Chip-on-Chip type SiP, for example, is realized by connecting a memory chip and a logic circuit chip to each other through micro-bumps formed on the chips with active surfaces of the chips being made to face each other on a Face-to-face basis.
Normally, in the Chip-on-Chip type SiP, a liquid resin called an underfill material is enclosed in an air gap defined between the chips connected to each other through the bumps for the purpose of protecting the bumps. The underfill material, for example, is enclosed in the air gap defined between the chips by utilizing a method as shown in FIG. 21. This method, for example, is described in Japanese Patent Laid-Open No. 2005-276879. That is to say, a first semiconductor chip 1 and a second semiconductor chip 2 (including diffusion layers, transistors, a wiring layer and the like (not shown)) are connected to each other through bumps 3. In this state, an underfill material 5 is supplied by using a needle 4. At this time, the underfill material 5 is dropped onto a position on a surface of the first semiconductor chip 1 and in the vicinity of the semiconductor chip 2. As a result, the underfill material 5 wetly spreads on the surface of the first semiconductor chip 1 to reach an end portion of the second semiconductor chip 2, and then penetrates from the end portion to an air gap defined between the first semiconductor chip 1 and the second semiconductor chip 2 by a capillary action. In addition, the underfill material 5 which has penetrated by the capillary action, as shown in FIGS. 22A and 22B, forms a fillet 6 which spreads toward bottom in an outer peripheral portion of the second semiconductor chip 2. After that, the underfill material 5 is cured by carrying out a heat treatment. As a result, each of the bumps 3 is prevented from cracking due to concentration of a stress, and an influence of an external stress such as moisture absorption is relaxed, thereby ensuring the reliability of the correction between the upper chip and the lower chip.